As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin-like field effect transistor (FinFET). A typical FinFET is fabricated with a thin “fin” (or fin structure) extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. It is beneficial to have a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFET devices include reducing the short channel effect and higher current flow.
As device structures become more dense, there have been problems associated with fabrication of FinFET devices. For example, conventional FinFET device fabrication methods are unable to provide varied profiles, such as a square profile, of facets (e.g., Si or SiGe facets) of the fin structure. Simply changing various process settings has proved incapable of significantly improving the ability to fabricate varied profiles. The facet profile affects a contact salicidation area, which in conventional FinFET devices may be smaller than desirable, resulting in higher than desirable salicide contact resistance, and thus poor device performance. Further, in conventional FinFET device fabrication methods, a fin structure height is limited by a fin structure width, for example, because of faceting. As devices become smaller, the fin structure height limitation further exacerbates the shrinking contact salicidation area issue. Accordingly, an improved FinFET device and improved method for fabricating a FinFET device is desired.